1. Field of the Invention
The present invention relates to an antireflection coating used in a semiconductor device manufacturing process and to a semiconductor device manufacturing method including a process of forming the same.
2. Description of the Background Art
In general, the interconnection in semiconductor devices is formed by pattern-etching a film of interconnection conductor such as metal, silicide, etc. The method in which resist is applied directly on the interconnection conductor film and the interconnection conductor film is directly etched using the resist as a mask is no longer in common use; the following method is widely used instead. That is to say, a silicon oxide film (also called an oxide film hereinafter) or a silicon nitride film (also called a nitride film hereinafter) is formed on the interconnection conductor film and the oxide film or the like is first patterned by using the resist. Subsequently the interconnection conductor film is pattern-etched by using the patterned oxide film etc. as a mask.
In this process, an antireflection coating (ARC) is provided to prevent the exposure light for exposing the resist from reflecting at a film lying under the resist. FIG. 45 is a schematic sectional view showing a semiconductor device (or a semiconductor substrate) 101P, which is used to explain a conventional antireflection coating 10P. The semiconductor device 101P has a tungsten silicide (WSi) film 4P for the gate electrode, an oxide film 3P, a nitride film 2P, an antireflection coating 10P and a resist 1P stacked in this order. The nitride film 2P is made of stoichiometric silicon nitride (Si3N4).
The antireflection coating 10P is composed of a single layer of silicon nitride formed by plasma CVD (Chemical Vapor Deposition: hereinafter the silicon nitride film is referred to also as a p-SiN film). The antireflection coating 10P is also called a p-SiN film 10P hereinafter using the same reference character. In order to allow the p-SiN film 10P to function as the antireflection coating, it is preferred that its complex index of refraction (nxe2x88x92ixc3x97k) approximately satisfy the conditions 1.5xe2x89xa6nxe2x89xa62.5, 0.2xe2x89xa6kxe2x89xa61.5. The characters n, k and i are, respectively, the real part and the imaginary part of the complex index of refraction and the imaginary number (imaginary unit).
It is assumed here that, for the p-SiN film 10P, n=2.13, k=0.83, and its film thickness is 47.5 nm (475 angstroms).
FIG. 46 is a contour diagram showing the results of calculation (simulation) of the reflectance R of the exposure light in the semiconductor device 101P using the p-SiN film 10P. The horizontal and vertical axes in FIG. 46 respectively show the film thickness of the oxide film 3P and that of the nitride film 2P in the semiconductor device 101P. The reflectance R was calculated considering the multiple reflection of the light, so that the calculated results almost perfectly agree with experimental results. While the calculation of the reflectance R assumes that the exposure light is at a wavelength of 248 nm, similar calculation results are obtained at other wavelengths.
It can be seen from FIG. 46 that the reflectance R varies between about 2 and 8% with the film thickness variations of the oxide film 3P and the nitride film 2P. The variation of the reflectance R directly affects the patterning dimensions of the resist. This is described below.
FIG. 47 is a schematic sectional view showing another semiconductor device 102P used to explain the antireflection coating 10P. The semiconductor device 102P has a polycrystalline silicon film 5P for the gate electrode, the oxide film 3P, the p-SiN film 10P, the resist 1P and a top antireflection coating (TARC) 6P stacked in this order.
FIG. 48 is a graph showing the results of calculation of the resist patterning dimension in the semiconductor device 102P using the p-SiN film 10P. The horizontal and vertical axes in FIG. 48 respectively show the thickness of the oxide film 3P of the semiconductor device 102P and the patterning dimension (line width) of the resist 1P; FIG. 48 shows the results of calculation at varied exposure light energies. The conditions used for exposure of the resist 1P are: NA (Numerical Aperture)=0.65; annular ⅔; exposure mask L/S (Line and Space) pattern 200 nm. It can be seen from FIG. 48 that the dimension of the resist 1P varies by 17 nm as the film thickness of the oxide film 3P varies.
While the two semiconductor devices 101P and 102P differ in detailed structure, they are common in that a transparent insulating film is provided under the antireflection coating 10P. Therefore the description above applies to both of the semiconductor devices 101P and 102P.
Achieving further size reduction of the semiconductor devices requires finer dimensional accuracy. For example, a semiconductor device with a line width of 130 nm is required to satisfy a total dimensional accuracy of about xc2x110% (13 nm), so that the above-described variation of the resist patterning dimension, caused by the film thickness variations of the oxide film 3P and nitride film 4P, must be restricted to about xc2x15 nm. That is to say, the existing process is insufficient.
A first aspect of the present invention is directed to an antireflection coating provided between an underlying layer and a resist in a semiconductor device manufacturing process. According to the first aspect, the antireflection coating comprises: a lower plasma silicon nitride film provided on the underlying layer, the lower plasma silicon nitride film being formed by a plasma chemical vapor deposition and containing more silicon than stoichiometric silicon nitride (Si3N4); and an upper plasma silicon nitride film provided on the lower plasma silicon nitride film, the upper plasma silicon nitride film being formed by the plasma chemical vapor deposition and containing more silicon than the stoichiometric silicon nitride (Si3N4); wherein the lower plasma silicon nitride film has a complex index of refraction in which the real part and the imaginary part have values respectively in the range of not less than 1.9 nor more than 2.5 and in the range of not less than 0.9 nor more than 1.7, and the lower plasma silicon nitride film has a thickness in the range of not less than 20 nm nor more than 60 nm, and wherein the upper plasma silicon nitride film has a complex index of refraction in which the real part and the imaginary part have values respectively in the range of not less than 1.7 nor more than 2.4 and in the range of not less than 0.15 nor more than 0.75, and the upper plasma silicon nitride film has a thickness in the range of not less than 10 nm nor more than 40 nm.
Preferably, according to a second aspect, in the antireflection coating, the complex index of refraction of the lower plasma silicon nitride film is (2.1xe2x88x92ixc3x971.2) and the thickness of the lower plasma silicon nitride film is 50 nm, and the complex index of refraction of the upper plasma silicon nitride film is (2.0xe2x88x92ixc3x970.3) and the thickness of the upper plasma silicon nitride film is 30 nm.
Preferably, according to a third aspect, the antireflection coating further comprises a silicon oxide film formed on the upper plasma silicon nitride film.
Preferably, according to a fourth aspect, in the antireflection coating, the silicon oxide film has a thickness of about 4 to 10 nm.
According to a fifth aspect, a semiconductor device manufacturing method comprises the steps of: (a) forming an underlying layer; (b) forming an antireflection coating on the underlying layer; and (c) forming a resist on the antireflection coating and patterning the resist through exposure and developing; the step (b) comprising the steps of (b-1) forming a lower plasma silicon nitride film on the underlying layer by a plasma chemical vapor deposition, the lower plasma silicon nitride film containing more silicon than stoichiometric silicon nitride (Si3N4), and (b-2) forming an upper plasma silicon nitride film on the lower plasma silicon nitride film by the plasma chemical vapor deposition, the upper plasma silicon nitride film containing more silicon than the stoichiometric silicon nitride (Si3N4), wherein the lower plasma silicon nitride film has a complex index of refraction in which the real part and the imaginary part have values respectively in the range of not less than 1.9 nor more than 2.5 and in the range of not less than 0.9 nor more than 1.7, and the lower plasma silicon nitride film has a thickness in the range of not less than 20 nm nor more than 60 nm, and wherein the upper plasma silicon nitride film has a complex index of refraction in which the real part and the imaginary part have values respectively in the range of not less than 1.7 nor more than 2.4 and in the range of not less than 0.15 nor more than 0.75, and the upper plasma silicon nitride film has a thickness in the range of not less than 10 nm nor more than 40 nm.
Preferably, according to a sixth aspect, in the semiconductor device manufacturing method, the complex index of refraction of the lower plasma silicon nitride film is (2.1xe2x88x92ixc3x971.2) and the thickness of the lower plasma silicon nitride film is 50 nm, and the refractive index of the upper plasma silicon nitride film is (2.0xe2x88x92ixc3x970.3) and the thickness of the upper plasma silicon nitride film is 30 nm.
Preferably, according to a seventh aspect, in the semiconductor device manufacturing method, the step (b-1) and the step (b-2) are continuously performed in the same chamber.
Preferably, according to an eighth aspect, in the semiconductor device manufacturing method, the step (b) further comprises a step (b-3) of exposing an exposed surface of the upper plasma silicon nitride film to a plasma of a gas which contains oxygen to form a thermal oxide film.
Preferably, according to a ninth aspect, the semiconductor device manufacturing method further comprises the steps of; (d) forming a silicon oxide film covering the upper and lower plasma silicon nitride films, and (e) applying at least one of an etching process and a polishing process to the silicon oxide film.
According to the first aspect, the reflectance of the exposure light can be reduced during the resist exposure so that the resist, and hence the underlying layer, can be accurately patterned. Moreover, the light intensity distribution of the standing wave of the exposure light produced in the resist can be improved to make the patterned resist less apt to break. Furthermore, since the lower and upper plasma silicon nitride films are formed by using plasma chemical vapor deposition, the two plasma silicon nitride films can be continuously formed in the same chamber. That is to say, the formation of the antireflection coating offers good productivity.
According to the second aspect, the reflectance of the exposure light can be reduced during the resist exposure, regardless of the film thickness of the underlying layer.
According to the third aspect, it is possible to prevent the lower and upper plasma silicon nitride films from lessening the effect of acid generated in a chemically amplified resist.
According to the fourth aspect, in the semiconductor device manufacturing method, the silicon oxide film is formed so thin that the silicon oxide film and the upper and lower plasma silicon nitride films can be removed without the need to perform separated process steps (i.e. they can be removed simultaneously).
According to the fifth aspect, the reflectance of the exposure light can be reduced in the step (c), so that the resist, and hence the underlying layer, can be accurately patterned. Also, the light intensity distribution of the standing wave of the exposure light produced in the resist can be improved to prevent the patterned resist from breaking.
According to the sixth aspect, the reflectance of the exposure light can be reduced during the resist exposure, independently of the film thickness of the underlying layer.
According to the seventh aspect, the formation of the antireflection coating offers good productivity.
According to the eighth aspect, the thermal oxide film prevents the lower and upper plasma silicon nitride films from lessening the acid effect of the chemically amplified resist. Also, in the semiconductor device manufacturing process, the thermal oxide film is formed so thin (about 4 nm) in the step (b-3) that the thermal oxide film and the upper and lower plasma silicon nitride films can be removed without the need for separated process steps (i.e. they can be removed simultaneously). Moreover, the step (b-3) uses a plasma of an oxygen-containing gas, so that the lower and upper plasma silicon nitride films and the thermal oxide film can be continuously formed in the chamber used to form the lower and upper plasma silicon nitride films, thus providing good productivity in the antireflection coating formation.
According to the ninth aspect, in the step (e), the upper and lower plasma silicon nitride films can be used as a stopper in the process of etching or/and polishing the silicon oxide film. Accordingly, the stoichiometric silicon nitride (Si3N4), which has conventionally been used as the stopper, can be formed thinner or removed. In general, the plasma silicon nitride film offers higher deposition rate than the stoichiometric silicon nitride, so that the stopper can be formed with good productivity. Also, in general, the plasma silicon nitride film produces smaller film stress than the stoichiometric silicon nitride, so that the film stress in the semiconductor device can be reduced.
The present invention has been made to solve the problems explained earlier, and a first object of the present invention is to provide an antireflection coating and a semiconductor device manufacturing method which enable the resist to be accurately patterned and also enable the resist to be formed in such shape as will not easily break.
A second object of the present invention is to provide an antireflection coating and a semiconductor device manufacturing method which can achieve the first object regardless of the film thickness of the underlying layer beneath the antireflection coating.
A third object of the present invention is to provide an antireflection coating and a semiconductor device manufacturing method which are suitable for use with a chemically amplified resist.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.